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ATmega128
SPI Status Register –
SPSR
Bit
Read/ W rite
Initial Value
7
SPIF
R
0
6
WCOL
R
0
5
–
R
0
4
–
R
0
3
–
R
0
2
–
R
0
1
–
R
0
0
SPI2X
R/ W
0
SPSR
? Bit 7 – SPIF: SPI Interrupt Flag
W hen a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI is
in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing the
corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first reading the
SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
? Bit 6 – WCOL: Write COLlision flag
The W COL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
W COL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with W COL set,
and then accessing the SPI Data Register.
? Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the ATmega128 and will always read as zero.
? Bit 0 – SPI2X: Double SPI Speed Bit
W hen this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI
is in Master mode (see Table 72 ). This means that the minimum SCK period will be 2 CPU clock
periods. W hen the SPI is configured as Slave, the SPI is only guaranteed to work at f osc /4 or
lower.
The SPI interface on the ATmega128 is also used for program memory and EEPROM down-
loading or uploading. See page 300 for SPI Serial Programming and verification.
SPI Data Register –
SPDR
Bit
7
6
5
4
3
2
1
0
MSB
LSB
SPDR
Read/ W rite
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
R/ W
Initial Value
X
X
X
X
X
X
X
X
Undefined
The SPI Data Register is a Read/ W rite Register used for data transfer between the register file
and the SPI Shift Register. W riting to the register initiates data transmission. Reading the regis-
ter causes the Shift Register Receive buffer to be read.
168
2467X–AVR–06/11
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